Fault-tolerant quantum computing software

Fault-tolerant experiments.
Available on your hardware today.

QECSync compiles logical qubit circuits onto physical devices using per-device surface-code decoders. Stop waiting for cleaner qubits.

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Per-device Decoder Tuning

Decoder weights calibrated to your hardware's specific noise model — not a generic off-the-shelf configuration.

Surface Code Native

Built from the ground up around surface code plaquette stabilizer measurements, supporting both MWPM and Union-Find decoders.

Hardware-Agnostic Compiler

Logical circuits compile to fault-tolerant gate sequences on superconducting, trapped-ion, and neutral atom backends.

Architecture

From logical circuit to physical execution

USER INPUT Logical Qubit Circuit ( Clifford + T gates, magic state protocol ) QECSYNC PLATFORM Surface-Code Compiler ↔ Per-device Decoder Engine ( MWPM / Union-Find ) HARDWARE Superconducting HARDWARE Trapped Ion HARDWARE Neutral Atom
Performance

Measured. Reproducible.

<1ms decoder latency per syndrome cycle
>99.5% logical error suppression vs. physical rate
6 hardware backends supported
7+ qubit connectivity topologies compatible

Performance varies by hardware configuration. All benchmarks on synthetic noise models. See benchmarks →

Workflow

How QECSync works

1

Import logical circuit

Submit any logical qubit circuit in standard gate notation (Clifford+T, OpenQASM). QECSync ingests the circuit and validates qubit connectivity requirements.

2

Compile and tune decoder

QECSync maps logical gates to fault-tolerant sequences, applies per-device noise characterization data, and tunes surface-code decoder weights for your hardware.

3

Run fault-tolerant experiments

Execute on target hardware with real-time syndrome decoding. Monitor logical error rates below the fault-tolerance threshold on your existing device.

Designed for

Research teams pushing the hardware frontier

Quantum hardware companies

Hardware engineers testing coherence at the gate layer

Your physical qubits are improving every quarter. QECSync lets you run logical qubit experiments on today's device, not tomorrow's idealized model.

  • Per-device calibration from raw noise characterization data
  • Configurable code distance scaling for coherence budgets
  • Decoder latency compatible with cryogenic control systems
National research labs

Program managers running logical qubit milestone experiments

National lab quantum programs require reproducible logical qubit demonstrations. QECSync provides the compiler and decoder infrastructure to hit those milestones.

  • Reproducible benchmark protocols on synthetic noise models
  • Python API compatible with existing quantum control stacks
  • Documentation and research-grade technical support
Research foundations

Grounded in surface code theory

QECSync's decoder and compiler are built on the mathematical foundations of topological quantum error correction — specifically the surface code threshold analysis, MWPM syndrome decoding, and Union-Find decoder variants documented in the published literature since Kitaev (2003) through Fowler et al. (2012) and subsequent algorithmic refinements.

We implement, test, and tune these algorithms against real device noise models — translating theoretical threshold predictions into practical, measurable fault-tolerance performance.

Research foundations →
physical error rate → logical error rate → below threshold above threshold ~1% threshold
Scope of the tool

Compiler and decoder software — that's the scope

QECSync does not manufacture quantum hardware. It does not operate a quantum cloud platform. It does not run classical simulation of quantum algorithms. QECSync is the compiler and decoder layer that sits between your logical circuit and your physical device — nothing outside that stack.

Ready to run fault-tolerant experiments on your hardware?

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Explore the documentation

Install QECSync, configure your noise model, and run your first fault-tolerant circuit in under 30 minutes.

Read the Docs