The fault-tolerance threshold is often cited as a binary: either your hardware is below the ~1% physical error rate, or it isn't. In practice, the threshold is not a hard cutoff but a function of your specific noise model, your decoder quality, and your code distance — and real hardware in 2025 occupies a range of positions relative to it that are worth understanding in detail.
This article examines where published hardware metrics from the quantum computing field stand relative to the surface-code threshold as of late 2025. We focus on two-qubit gate fidelity and T2 coherence time because these are the dominant inputs to logical error rate under a surface-code compilation model. All figures are drawn from publicly available vendor publications, academic papers, and conference presentations — not from private benchmarks.
What the threshold actually means
The fault-tolerance threshold theorem (Aharonov and Ben-Or 1997; Knill, Laflamme, and Zurek 1998) states that if physical error rates are below a threshold value, then arbitrarily long quantum computations can be performed with arbitrarily small logical error rate by increasing code distance and accepting the overhead. Above the threshold, adding more qubits makes the logical error rate worse, not better.
For the planar surface code under independent depolarizing noise, the threshold is approximately 1.1% (Fowler et al. 2012). This is the two-qubit gate error rate at which logical error rate curves for d=3, d=5, d=7, d=9 all converge — below this rate, higher distance curves sit below lower distance curves (error suppression with distance); above it, they cross (distance is counterproductive).
Two caveats that matter for interpreting real hardware results:
- Measurement error contributes separately. The syndrome cycle includes ancilla qubit readout, which has its own assignment error rate. A device with 0.3% two-qubit gate error but 5% readout error still has poor QEC performance. Effective threshold analysis requires treating gate error and measurement error as separate parameters.
- Spatially correlated noise lowers the effective threshold. The 1.1% figure assumes errors are spatially uncorrelated. Real superconducting devices have qubit-to-qubit crosstalk (ZZ coupling) that introduces spatial correlations. Correlated noise lowers the effective threshold, which is why per-device decoder calibration matters even on devices that appear to be well below threshold on average.
Superconducting transmon: current published state
As of late 2025, leading superconducting processors have demonstrated median two-qubit gate error rates in the 0.2–0.5% range for CX and ECR gate sets, with best-qubit-pair performance approaching 0.1%. T2 coherence times range from 50 µs to 300+ µs depending on qubit quality and device vintage.
Median two-qubit gate fidelity at 0.3–0.5% places these devices roughly 2–5× below the depolarizing threshold. That margin sounds comfortable, but it is consumed quickly when you account for measurement error (typically 0.5–2% per qubit), crosstalk penalties, and the fact that the worst qubits on a device — not the median — set the ceiling for effective code distance.
A useful framing: for a d=5 surface code (49 physical qubits), the logical error rate at p=0.003 median two-qubit error is approximately 4×10⁻⁴ per syndrome cycle with a well-tuned decoder. At p=0.005 (still well below threshold), it rises to approximately 2×10⁻³. A factor of 1.7× in physical error rate produces a factor of 5× in logical error rate — the exponential suppression works in both directions near the threshold.
Trapped-ion: high fidelity, slow gates
Trapped-ion systems have demonstrated two-qubit gate fidelities of 99.5–99.9% (0.1–0.5% error rate) on small ion chains, placing them well below the depolarizing threshold on the gate fidelity axis. Coherence times of seconds give a comfortable error budget for syndrome cycle depth.
The practical constraint is gate speed. A Mølmer-Sørensen gate on a typical trapped-ion system takes 100–500 µs. A syndrome cycle on a 17-qubit d=3 surface code requires approximately 20–30 two-qubit gates, placing the cycle time at 2–15 ms. This is not a threshold problem; it is a circuit throughput problem. For research experiments that need to run many logical operations, the effective computation rate is constrained by gate speed rather than fidelity.
For experiments that measure logical qubit memory — how long a logical state survives N syndrome cycles — trapped-ion hardware in 2025 can demonstrate exponential error suppression from d=3 to d=5 with high statistical confidence, as several published results have shown. The quality of this suppression depends critically on the decoder, which is where per-device calibration in QECSync contributes even on high-fidelity platforms.
Neutral atom: emerging results
Neutral atom platforms have published two-qubit gate fidelities in the 99–99.8% range (0.2–1% error rate) as of 2025, with rapid improvement trajectory over 2023–2025. Some demonstrations achieve mid-circuit measurement, a prerequisite for real-time QEC.
Key caveat for neutral atom QEC: the error model differs meaningfully from the depolarizing assumption. Atom loss (leakage) is a dominant error channel in some platforms. Leakage errors — where a qubit leaves the computational subspace entirely — require different treatment in the decoder than standard Pauli errors. A surface-code decoder not configured to handle leakage will underperform on these platforms compared to what gate fidelity numbers alone would predict.
The decoder's role in effective threshold
An underappreciated point: the fault-tolerance threshold is not purely a hardware number. It also depends on decoder quality. The theoretical 1.1% threshold is derived assuming an optimal decoder (one that finds the maximum-likelihood correction, not just minimum-weight perfect matching). MWPM is near-optimal but not exactly optimal; Union-Find is further from optimal. The practical threshold for a given decoder is somewhat below the theoretical maximum.
Per-device weight calibration partially recovers this gap. A device with spatially non-uniform noise running an uncalibrated decoder sees an effective threshold lower than the theoretical value because the decoder is making systematically suboptimal matching decisions. Incorporating measured per-qubit and per-gate error rates into the edge weight matrix brings the effective threshold closer to the theoretical value for that noise model.
Our internal benchmarks on synthetic noise models calibrated from published hardware parameters show a consistent 15–30% reduction in logical error rate when using per-device calibrated weights versus uniform weights, at physical error rates between 0.2% and 0.8%. This improvement is available to any hardware platform at the current threshold margin.
Practical recommendations for 2025
For research groups planning logical qubit experiments on current hardware:
- Start at d=3 or d=5 on your best available qubits. Characterize logical error rate per syndrome cycle first.
- Do not attempt d=7 or higher before demonstrating suppression from d=3 to d=5. The exponential suppression should be measurable before adding more physical resources.
- Treat your worst qubit pair's two-qubit gate fidelity as your effective error rate, not the median. The surface code's logical error rate is driven by the worst error chains, which run through the highest-error links.
- Run your calibration protocol (randomized benchmarking or cross-entropy benchmarking) immediately before the QEC experiment, not from a cached calibration file. Gate fidelities drift on timescales of hours to days on superconducting devices.
- If your decoder accepts per-qubit noise parameters, use them. The improvement over uniform-weight decoding on non-uniform hardware is significant enough to affect whether your d=5 logical error rate is clearly better than d=3.
For the latter point, the technology page describes how QECSync's calibration pipeline works in detail, and the hardware integration guide describes the calibration data format QECSync accepts.