In-depth articles on quantum error correction, decoding algorithms, hardware noise, and fault-tolerant circuit compilation.
A practical introduction to the planar surface code for engineers who know quantum circuits but haven't worked with topological codes. Covers stabilizer generators, X and Z plaquettes, and how syndrome measurements form the input to a decoder.
Read article →A practical comparison of Minimum Weight Perfect Matching and Union-Find for surface-code syndrome decoding. When does the latency advantage of Union-Find outweigh the accuracy advantage of MWPM? We work through the tradeoff by code distance and noise regime.
Read article →What does "hardware-agnostic" actually mean when compiling fault-tolerant circuits? We walk through the DeviceSpec abstraction and explain how the same logical circuit compiles to different physical schedules depending on native gate set, connectivity topology, and T2 coherence time.
Read article →Published two-qubit gate fidelities and T2 coherence times from superconducting and trapped-ion vendors as of late 2025. We analyze which devices are operating close to the surface-code threshold and what the margin looks like.
Read article →How QECSync approaches per-device noise characterization: randomized benchmarking to get per-qubit gate error rates, cross-entropy benchmarking for two-qubit errors, and how that data flows into the MWPM edge weight matrix.
Read article →Measuring the logical error rate of a surface-code logical qubit is more subtle than measuring physical gate fidelity. We describe the benchmark protocol QECSync uses, how to isolate decoder contribution from hardware contribution, and what numbers to report.
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